1. Field Of The Invention
The present invention relates to a data-line sense amplifier used to sense and amplify the output from a charge transfer sense amplifier of a dynamic random access memory, and more particularly to the structure of a data-line sense amplifier that has low power and high speed and includes a memory writing function.
2. Description of Related Art
The form and structure of a dynamic random access memory (DRAM) is well known in the art. Referring to FIGS. 1 and 2, a memory cell is constituted of a capacitor C.sub.1 connected to a reference voltage and a gating metal oxide semiconductor transistor (MOST) Q.sub.1. The gate of the MOST Q.sub.1 is controlled by the word line control signal wl.sub.0 . . . wl.sub.n-1. The word line control signal wl.sub.0 . . . wl.sub.n-1 allows the MOST Q.sub.1 to conduct or not conduct a voltage present on a bit line bl0 or bl0n.
A plurality of memory cells mc.sub.0 . . . mc.sub.n/2-1 and mc.sub.n/2 . . . mc.sub.n-1 form two arrays array1 and array2. Each bit line bl0 and bl0n is connected to a precharge control MOST Q.sub.2 and Q.sub.3 respectively. The control line precharge activates to precharge control MOST Q.sub.2 and Q.sub.3 to precondition the bit lines bl0 and bl0n to a voltage Vref.sub.2. Vref.sub.2 is generally equal to a magnitude of one half the difference of the power supply of the DRAM and the ground reference.
To detect the presence of charge in a memory cell, for instance mc.sub.1, word line wl1 is activated to cause the MOST Q.sub.1 of mc.sub.1 to conduct. Any charge that is present on C.sub.1 will be transferred to bit line bl0n. Since no word line wl.sub.n/2 . . . wl.sub.n-1. in array2 is activated, the voltage present on bit line bl0 will be at Vref.sub.2. The bit line sense amplifier will compare the voltage on the bit line bl0n to the voltage on the bit line bl0 which Is wl.sub.0 . . . wl.sub.n-1. If there is no charge on the capacitor C.sub.1 of mc.sub.1, then the bit line bl0n will have a voltage less than Vref.sub.2. if there is a charge on the capacitor C.sub.1 of mc.sub.1, then the bit line bl0n will have a voltage larger than Vref.sub.2. The bit line sense amplifier will place a logical "1" on the data line dl0n and a logical "0" on the data line dl0, if there is a charge on capacitor C.sub.1 of mc.sub.1. If the capacitor C.sub.1 of mc.sub.1 is not charged, the sense amplifier will place a logical "0" on the data line dl0n and a logical "1" on the data line dl0.
To write data to the memory, which is the storing of a charge on the capacitor C.sub.1, the sense amplifier is deactivated and the write circuit is activated. For instance, if memory cell mc.sub.1 is to be written, the data would be placed on data line dl0n. The write circuit would couple data line dl0n to the bit line bl0n. The word line wl.sub.1 would activate Q.sub.1 of mc.sub.1 and capacitor C.sub.1 of mc.sub.1 would be charged for a logical "1" on the latched data line dl0n and would be discharged for a logical "0" on the data line dl0n.
Many DRAM configurations require that the sense amplifier and the write circuit be geographically separate, thus complicating the layout of the DRAM.
FIG. 3 illustrates a differential data line sense amplifier. MOST's N473 and N474 and MOST's N542 and N543 (MOST's with an N designation will be N-type metal oxide semiconductors while MOST's with a P designation will be P-type metal oxide semiconductors) for two differential pair of transistors for two operational amplifiers op-amp1 and op-amp2. MOST's N471 and N541 form the current sources for the two operational amplifiers op-amp1 and op-amp2. MOST's P476 and P475 and MOST's P537 and P536 form active loads for the operational amplifiers op-amp1 and op-amp2. The inverting input INinv.sub.1 of op-amp1 and the noninverting input IN.sub.2 of op-amp2 are connected to the data line dl0 and the data line dl0n is connected to the noninverting input IN.sub.1 of op-amp1 and to the inverting input Ininv.sub.2 of op-amp2. The output OUT.sub.1 of operational amplifier op-amp1 is connected to latched data line dll0n and the output OUT.sub.2 of operational amplifier op-amp2 is connected to latched data line dll0.
The differential sense amplifier consumes a large amount of area on an integrated circuit, since two complete operational amplifiers are required to amplify signals on the data lines to levels sufficient to drive I/O lines.
A latching data line sense amplifier is illustrated in FIG. 4. MOST's N33 and N34 and MOST's P32 and P31 are coupled together to form cross coupled latching amplifiers. MOST N35 and MOST P60 perform the gating function for the cross coupled latching amplifiers.
The data line dl0 and the latched data line dll0 are connected to the drains of MOST's P32 and N33 and to the gates of MOST's P31 and N34. The data line bl0 and the latched data line dll0n are connected to the drains of MOST's P31 and N34 and to the gates of MOST's P32 and N33.
This cross coupled configuration has positive feedback causing the cross coupled amplifiers to have their outputs latch at either a voltage that is approximately the voltage power supply V.sub.DD or the ground reference voltage GND. As an example, if data line dl0n starts to rise above the precharge level of Vref.sub.2, the MOST N33 will start to conduct and MOST P32 will start to turn off, thus discharging data line dl0 from the precharge level. This will start MOST P31 to conduct and MOST N34 to turn off and point B will increase in voltage higher than the level than that of data line dl0n. This positive feedback will continue until the voltage at point A is a minimum or very close to the ground reference voltage GND, and the voltage at point B is at a maximum or at approximately the voltage power supply V.sub.DD. This state will be maintained as long as the latched sense amplifier is being activated.
The activation of the latched sense amplifier is controlled by the read signals rbs and rbsn. The read signal rbs is connected to the gate of MOST N35 and the read signal rbsn is connected to the gate of MOST P60. When the read signal rbs is at a logical "1" and rbsn is at a logical "0," the latched sense amplifier is active and when the read signal rbs is at a logical "0" and rbsn is at a logical "1 ," the latched sense amplifier is not active. When the latched sense amplifier is active, a relatively large amount of power is consumed because the outputs approach the voltage power supply V.sub.DD or the ground reference voltage GND. Additionally, the timing of the read signals rbs and rbsn is critical.
The latched sense amplifier as described above is similar to those incorporated in U.S. Pat. No. 5,300,839 (Kowahara, et al.), U.S. Pat. No. 5,367,481 (Takase, et al.), U.S. Pat. No. 5,984,202 (Kowahara, et al.), U.S. Pat. No. 4,947,376 (Arimoto, et al.), and U.S. Pat. No. 4,694,205 (Shu, et al.).
U.S. Pat. No. 5,434,821 (Watanabe, et al.) describes a bit line sense amplifier that is used to detect charge from a capacitor within a DRAM memory cell.